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2009 Microchip Technology Inc.

DS39636D-page 129

PIC18F2X1X/4X1X

13.2

Timer3 16-Bit Read/Write Mode

Timer3 can be configured for 16-bit reads and writes

(see Figure 13-2). When the RD16 control bit

(T3CON<7>) is set, the address for TMR3H is mapped

to a buffer register for the high byte of Timer3. A read

from TMR3L will load the contents of the high byte of

Timer3 into the Timer3 High Byte Buffer register. This

provides the user with the ability to accurately read all

16 bits of Timer1 without having to determine whether

a read of the high byte, followed by a read of the low

byte, has become invalid due to a rollover between

reads.

A write to the high byte of Timer3 must also take place

through the TMR3H Buffer register. The Timer3 high

byte is updated with the contents of TMR3H when a

write occurs to TMR3L. This allows a user to write all

16 bits to both the high and low bytes of Timer3 at once.

The high byte of Timer3 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer3 High Byte Buffer register.

Writes to TMR3H do not clear the Timer3 prescaler.

The prescaler is only cleared on writes to TMR3L.

13.3

Using the Timer1 Oscillator as the

Timer3 Clock Source

The Timer1 internal oscillator may be used as the clock

source for Timer3. The Timer1 oscillator is enabled by

setting the T1OSCEN (T1CON<3>) bit. To use it as the

Timer3 clock source, the TMR3CS bit must also be set.

As previously noted, this also configures Timer3 to

increment on every rising edge of the oscillator source.

The Timer1 oscillator is described in Section 11.0

“Timer1 Module”.

13.4

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and overflows to 0000h. The

Timer3 interrupt, if enabled, is generated on overflow

and is latched in interrupt flag bit, TMR3IF (PIR2<1>).

This interrupt can be enabled or disabled by setting or

clearing the Timer3 Interrupt Enable bit, TMR3IE

(PIE2<1>).

13.5

Resetting Timer3 Using the CCP

Special Event Trigger

If either of the CCP modules is configured to use Timer3

and to generate a special event trigger in Compare mode

(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this

signal will reset Timer3. It will also start an A/D conversion

if the A/D module is enabled (see Section 14.3.4

“Special Event Trigger” for more information).

The module must be configured as either a timer or

synchronous counter to take advantage of this feature.

When used this way, the CCPR2H:CCPR2L register

pair effectively becomes a period register for Timer3.

If Timer3 is running in Asynchronous Counter mode,

the Reset operation may not work.

In the event that a write to Timer3 coincides with a

special event trigger from a CCP module, the write will

take precedence.

TABLE 13-1:

REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note:

The special event triggers from the CCP2

module will not set the TMR3IF interrupt

flag bit (PIR1<0>).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR2

OSCFIF

CMIF

—

BCLIF

HLVDIF

TMR3IF

CCP2IF

PIE2

OSCFIE

CMIE

—

BCLIE

HLVDIE

TMR3IE

CCP2IE

IPR2

OSCFIP

CMIP

—

BCLIP

HLVDIP

TMR3IP

CCP2IP

TMR3L

Timer3 Register, Low Byte

TMR3H

Timer3 Register, High Byte

T1CON

RD16

T1RUN

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS TMR1ON

T3CON

RD16

T3CCP2

T3CKPS1 T3CKPS0 T3CCP1

T3SYNC

TMR3CS TMR3ON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

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